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High Speed Dual Rail Domino Logic with N-Device for Precharge

IP.com Disclosure Number: IPCOM000113207D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Liu, MN: AUTHOR

Abstract

In traditional dynamic logic design, two dynamic logic blocks have to be separated by a latch or register in order to prevent malfunction during evaluation. Domino logic has been introduced in order to cascade a set of dynamic logic blocks. However, traditional domino logic can only implement non-inversion logic if only N-devices are used for high speed discharging. Another way to cascade dynamic logic blocks directly is to skew the clock signal. The major set-back to this approach is that a tremendous amount of design and verification efforts are involved and designers are facing a high risk of failure due to insufficient best case process parameters.

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High Speed Dual Rail Domino Logic with N-Device for Precharge

      In traditional dynamic logic design, two dynamic logic blocks
have to be separated by a latch or register in order to prevent
malfunction during evaluation.  Domino logic has been introduced in
order to cascade a set of dynamic logic blocks.  However, traditional
domino logic can only implement non-inversion logic if only N-devices
are used for high speed discharging.  Another way to cascade dynamic
logic blocks directly is to skew the clock signal.  The major
set-back to this approach is that a tremendous amount of design and
verification efforts are involved and designers are facing a high
risk of failure due to insufficient best case process parameters.

      This new circuit structure utilized dual rails in Domino logic
such that all outputs of each logic block are precharges low which in
turn cut off all N-devices in subsequent logic blocks.  When a block
is evaluated, the outputs will conditionally go high.  Each N-device
in sequence can make at most one discharge transition.  One major
advantage of this structure is to make the delay of discharge circuit
independent of clock timing while cascading any number of logic
stages, as long as the total propagation delay is less than a given
timing requirement.

      Another technique involved in this structure is the precharge
scheme.  As all inputs are set to low during precharge, more internal
nodes than that in traditional dynamic c...