Browse Prior Art Database

Multiple Memory Refresh Operation for Personal Computers

IP.com Disclosure Number: IPCOM000113220D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 129K

Publishing Venue

IBM

Related People

Chan, FL: AUTHOR [+5]

Abstract

Described is an architectural implementation for Micro Channel* (MC) single bus Personal Computers (PCs) to improve system performance by providing multiple refresh of memory. Timing charts are used to show how the technique reduces the memory refresh bandwidth and increases the bus bandwidth available to the PCs microprocessor.

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Multiple Memory Refresh Operation for Personal Computers

      Described is an architectural implementation for Micro Channel*
(MC) single bus Personal Computers (PCs) to improve system
performance by providing multiple refresh of memory.  Timing charts
are used to show how the technique reduces the memory refresh
bandwidth and increases the bus bandwidth available to the PCs
microprocessor.

      With the increasing performance of microprocessors and with the
use of internal cache, the ability to perform instructions has caused
the external bus to be a restriction in the PC operation.  In turn,
the need for the microprocessor to utilize the external bus
increases.  As a result, any improvement in the external support
logic to improve the microprocessor bandwidth helps to improve system
performance.  In the prior art of single bus MC systems, every time a
MC refresh was executed in the system, the microprocessor was put
into a hold state.  For those systems, refresh cycles could take up
to 5% of the system bandwidth.

      The concept described herein provides a means whereby the
microprocessor is in the hold state only one time for every three MC
refresh periods.  Therefore, the microprocessor bandwidth can be
improved up to 4%.  The MC refresh period is kept the same for
hardware compatibility.

      Refresh of memory in PC systems, such as the IBM PS/2, is
typically performed every 15.6 microseconds.  Every time the refresh
cycle is executed, the microprocessor complex is on hold and the
refresh cycle can take up to 5% of the system bandwidth.  Optional
bits in the registers allow refresh cycles to memory to be performed
in short bursts of multiple cycles during one MC refresh period.

      The concept described herein enables three multiple refresh
cycles in one MC refresh period, thereby eliminating the need to hold
the microprocessor in the next two MC refresh cycles.  MC refresh
cycles will continue to be performed at the same rate as pr...