Browse Prior Art Database

Virtual Associative Mapping Cache Using Direct Mapping Hardware

IP.com Disclosure Number: IPCOM000113222D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Shimizu, S: AUTHOR

Abstract

This article describes a mechanism to virtually realize an 'associative mapping cache' scheme by using a direct mapping cache hardware. By the disclosed mechanism, a direct mapping cache hardware which has various advantages such as simple hardware scheme and hence a faster access time, can provide a higher hit ratio which is equal to that of an associative mapping cache hardware.

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Virtual Associative Mapping Cache Using Direct Mapping Hardware

      This article describes a mechanism to virtually realize an
'associative mapping cache' scheme by using a direct mapping cache
hardware.  By the disclosed mechanism, a direct mapping cache
hardware which has various advantages such as simple hardware scheme
and hence a faster access time, can provide a higher hit ratio which
is equal to that of an associative mapping cache hardware.

      A physical cache uses a physical address for its addressing,
and the physical address is provided by an address translation
hardware which translates a virtual address to a physical address
using an address translation table provided by a memory management
software of an operating system (Figure).  The disclosed mechanism
uses this fundamental and common scheme of the address translation in
a sophisticated manner, for virtually realizing an associative
address mapping on a direct mapping cache hardware.  The detailed
mechanism is described below.

      In the Figure, the lower M bits both of the virtual and
physical addresses represent an offset in a page.  The upper L bits
of the virtual address which represent a virtual page number are
translated to a physical page number of the physical address by the
address translation hardware.  The lower R bits of the physical
address are used as a byte address in a cache line.  The middle Q
bits are used for addressing a cache line in the cache.  And the
upper...