Browse Prior Art Database

Expansion Logic for Peripheral Component Interconnect Bus Arbitration Devices

IP.com Disclosure Number: IPCOM000113236D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Begun, RM: AUTHOR [+2]

Abstract

Disclosed is a mechanism whereby computer systems employing the Peripheral Component Interconnect (PCI) bus can efficiently cascade PCI REQ#/GNT# arbitration pairs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Expansion Logic for Peripheral Component Interconnect Bus Arbitration
Devices

      Disclosed is a mechanism whereby computer systems employing the
Peripheral Component Interconnect (PCI) bus can efficiently cascade
PCI REQ#/GNT# arbitration pairs.

      The multiple bus devices that the PCI bus supports are
connected via a common PCI bus.  To gain access to this bus, each
device uses a request/grant protocol.  This protocol uses the
REQ#/GNT# signals as documented in the PCI specification (*).  The
multiple REQ#/GNT# pairs are then connected to a central arbitration
resource.  This central resource accepts all REQ#/GNT# pairs and
determines which PCI device will be allowed to access the PCI bus at
the next available opportunity.  There may be cases, however, where
the arbitration resource does not provide a sufficient number of
arbitration pair inputs.

      A single REQ#/GNT# pair can be expanded to two pairs by adding
PCI ARB EXPANDER logic as shown in the Figure.

      This PCI Arbitration Expander Logic can be described as a
series of logic equations.  These equations describe a state machine
that tracks the two REQ#/GNT# pair inputs (REQ1A#/GNT1A# and
REQ1B#/GNT1B# above) from the PCI devices, and generates a single
REQ#/GNT# pair output (REQ1#/GNT1# above), which is then connected to
the central arbitration resource.

      The above logic can be implemented as a synchronous Moore state
machine, which delays the output transitions one PCI...