Browse Prior Art Database

Single Clock Distribution with Built-In Test Capability

IP.com Disclosure Number: IPCOM000113248D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+4]

Abstract

Described is a hardware circuit implementation that distributes a primary clock frequency and re-creates a diagnostic Built-In Self Test (BIST) capability. The circuitry is designed to reduce overall clock distribution demands of Very Large Scale Integrated (VLSI) circuits.

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Single Clock Distribution with Built-In Test Capability

      Described is a hardware circuit implementation that distributes
a primary clock frequency and re-creates a diagnostic Built-In Self
Test (BIST) capability.  The circuitry is designed to reduce overall
clock distribution demands of Very Large Scale Integrated (VLSI)
circuits.

      In prior art, VLSI circuitry required BIST to run diagnostics
at frequencies to meet Reliability and Serviceability (RAS)
requirements.  Several BIST signals were required to be distributed
with the same tolerances as the chip's functional clock.  This
required additional chip areas to distribute the test clocks.  The
functional and test clock generation was centrally located in the
clock macro.  This allowed a single clock generation source as well
as minimal distribution of test control lines needed to create test
clocks at the macro.  This technique required a large chip area for
global clock distribution since the BIST clocks had the same clock
skew and clock dead time specifications as the functional clock
signals.  Additional resources were needed to assure that the test
clock distribution met the stringent requirements of the functional
clock distribution.

      The concept described herein provides a method of reducing the
overall clock distribution demands on the chip resources by
distributing a single clock phase to all of the chip macros.  The
test clocks and functional clocks are re-created at the macro level
to meet clock skew and dead time control.

      The Figure sho...