Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Synchronization System Using Delay Elements

IP.com Disclosure Number: IPCOM000113250D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 78K

Publishing Venue

IBM

Related People

Inazumi, J: AUTHOR

Abstract

Disclosed is a synchronization system which uses a string of delay elements for both measuring offset time and adding compensation time. This method does not require any faster clock than base clock to synchronize signal. Delay time is self-aligned and no adjusting at manufacturing is required.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Synchronization System Using Delay Elements

      Disclosed is a synchronization system which uses a string of
delay elements for both measuring offset time and adding compensation
time.  This method does not require any faster clock than base clock
to synchronize signal.  Delay time is self-aligned and no adjusting
at manufacturing is required.

      Fig. 1 shows an example of this system.  Figs. 2 and 3 show
signal example of Fig. 1.  S is a reference signal which shows
synchronization timing at the rising edge.  Block A is driven by
clock C and generates P, P1, R, U and D.  Block B receives S, P1, R,
U and D and then outputs synchronized signal V.  P is a signal which
shows sampling of rising edge of S by clock C. R is a signal which
toggles by clock C. P1 is a signal which shows latched level of R
when P is high.  D is a Data signal which is to be synchronized in
block B. U is a window signal which shows separation timing between S
and D. T0 is cycle time of clock C. T6 is time between rising edge
(T1) of S and signal transient timing of R before T1.  T7 is
compensation time for V to D.

      Fig. 4 shows an example of block B. Block B1 is a selector
which passes R instead of D when U is high.  Block B2 is a string of
delay elements.  B2 outputs delayed signals at each terminals of
elements.  (M1, M2, M3, ...  represent each delayed signals.)

      Block B3 is a determiner which outputs selection signal to
block B4.  Block B4 is a select...