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Protecting CMOS Circuits in a 3- and 5-Volt Mixed Signal Environment

IP.com Disclosure Number: IPCOM000113253D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 103K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+5]

Abstract

Disclosed is a method for limiting the voltage excursions of inputs to 3-volt CMOS circuits in an environment with both 3-volt and 5-volt signals, without requiring power sequencing or special power supply sensing means.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Protecting CMOS Circuits in a 3- and 5-Volt Mixed Signal Environment

      Disclosed is a method for limiting the voltage excursions of
inputs to 3-volt CMOS circuits in an environment with both 3-volt and
5-volt signals, without requiring power sequencing or special power
supply sensing means.

      Advanced CMOS VLSI circuit chips have limits to the voltage
excursions which can occur on the I/O pads of the chips without
causing circuit latch-up and long-term reliability problems.

      Fig. 1 is a schematic view of a circuit in a CMOS VLSI chip 10
using a standard clamping method, in which, under an over-voltage
condition at I/O pad 11, a clamping diode 12 returns current to a
positive power supply providing a reference voltage VREF on reference
voltage pad 14.  This method limits a transient voltage excursion on
I/O pad 11 to a level that does not damage the silicon in, for
example, receiver circuit 16.  The circuit also includes conventional
control inputs 18 for the output stage of a CMOS tri-state bus
driver.  A number of additional clamping diodes 20, attached to
similar bus driver circuits, are also connected to reference voltage
pad 14.  Each clamping diode 20 is connected to another I/O pad (not
shown) on which a signal is received.  With VCC equal to 3.3 volts,
the reference voltage VREF is 3.3 volts if only a 3.3-volt signal
level is applied to I/O pad  11.  If either a 3.3-volt signal or a
5.0-volt signal may be applied to I/O pad 11, VREF is 5 volts.

      When this approach is used in an environment of both 3.3-volt
and 5.0-volt signal levels with reference voltage pad 14 connected to
a 5.0-volt power supply, a number of disadvantages are encountered.
Since the 3.3-volt and 5.0-volt signal levels come from different
power supply circuits, it is possible that the 5.0-volt power supply
may fail while  the 3.3-volt power supply remains operational.  In
this event, control inputs 18 can be expected to remain active, since
they operate from 3.3-volt power, and a 3.3-volt input signal to I/O
pad 11 can also occur.  However, the failure of the 5.0-volt power
supply drives reference voltage pad 11 to electrical ground, so that
a signal on I/O pad 11 is clamped to ground.  This means that all of
the current available in normal signals, without voltage transients,
will flow to ground, resulting in a current flow which is high enough
to cause physical damage to various circuits.  A transient problem of
this kind can occur while electrical power is switched on or off, if
the 5.0-volt power supply is allowed to turn on after the 3.3-volt
power supply, or if the 3.3-volt power supply switches off after the
5.5-volt power supply. ...