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Reservation Structure to Support Atomic Memory Accesses at the Memory Directory Maintaining Transparency to Memory for Shared Caches when Executing Atomic Instruction in MP Systems

IP.com Disclosure Number: IPCOM000113255D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Cheng, K: AUTHOR [+3]

Abstract

The pair of load-reserve (larx) and store-conditional (stcx) instructions are implemented to provide atomic updates of a storage location from multiple processors. In a directory-based MP system with L1 and L2 caches, multiple L1 caches can be sharing an L2 cache. Normally a memory module can handle any memory access from an L2 cache without knowing the specific processor, e.g., processor id, issuing the request. However, the reservation is on a processor basis and any bookkeeping of the events at the memory must be on a processor basis also, e.g., what reservation a processor currently has. Therefore, a direct implementation of the atomic instructions may require changes of the request format and MP protocols because they may carry processor id instead of just L2 id. This can substantially complicate the protocols.

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Reservation Structure to Support Atomic Memory Accesses at the Memory
Directory Maintaining Transparency to Memory for Shared Caches when
Executing Atomic Instruction in MP Systems

      The pair of load-reserve (larx) and store-conditional (stcx)
instructions are implemented to provide atomic updates of a storage
location from multiple processors.  In a directory-based MP system
with L1 and L2 caches, multiple L1 caches can be sharing an L2 cache.
Normally a memory module can  handle any memory access from an L2
cache without knowing the specific processor, e.g., processor id,
issuing the request.  However, the reservation is on a processor
basis and any bookkeeping of the events at the memory must be on a
processor basis also, e.g., what reservation a processor currently
has.  Therefore, a direct implementation of the atomic instructions
may require changes of the request format and MP protocols because
they may carry processor id instead of just L2 id.  This can
substantially complicate the protocols.

      Disclosed is a scheme to implement the larx and stcx atomic
instructions; the scheme allows the memory to be completely
transparent of the number of processors sharing the L2 caches.  The
basic implementation includes a reservation register at each CPU and
one corresponding register at the L2 cache.

      Each memory module has a table of n memory reservation
registers (mrr); each register contains the following fields: a valid
bit, a line id, and one p-bit per L2 cache.  The p-bit indicates if
the corresponding L2 cache has a reservation.  The table is keyed on
a cache line basis instead of on a processor basis, i.e., all the
processors reserving the same line go to the same register.  The
register contains one p bit for each L2 cache accessing the memory
module.  Each table entry also has a valid (v) bit to speed up the
table entry look-ups.  A request from an L2 cache to a memory module
is provided to clear a reservation.

      The following operations of the atomic instructions assume that
all of the reserved variables are cacheable; the non-cacheable
variables can be easily generalized.  The operations at the L1 cache
or at the processors are not part of what is herewith disclosed; they
are included here for completeness.  Also, it is assumed that the
line sizes at the L1 caches and L2 caches are the same.  The
granularity of reservation is a line and a line containing a reserved
variable is called a reserved line.

      Executing a larx is the same as that of a load except that...