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Restoration of Micro Channel Control Signals during Arbitration

IP.com Disclosure Number: IPCOM000113279D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Arimilli, JF: AUTHOR [+3]

Abstract

This disclosure illustrates a simple, generic method of restoring any bus' control signals during exchange of ownership. Since RS/6000's* use the Micro Channel* bus, it is used as an example here. Using this method of combined active and passive restoration, the Micro Channel arbitration time can be reduced from 400 ns to 100 ns in a fully loaded 8 slot configuration.

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Restoration of Micro Channel Control Signals during Arbitration

      This disclosure illustrates a simple, generic method of
restoring any bus' control signals during exchange of ownership.
Since RS/6000's* use the Micro Channel* bus, it is used as an example
here.  Using this method of combined active and passive restoration,
the Micro Channel arbitration time can be reduced from 400 ns to 100
ns in a fully loaded 8 slot configuration.

      The Micro Channel contains many control signals which need not
be driven by all bus masters.  This allows each master to achieve an
optimal cost/performance target by only providing a subset of the
Micro Channel features.  The system board contains pullup resistors
(as required by the Micro Channel Architecture) on all of these
control signals in order to passively restore these signals during
transfer of bus ownership from one master to another.  This is a
common configuration adopted by many expansion and IO buses.
However, the RC restore time for these control signals in a worst
case system can be significant (400 ns in a 8 slot MCA server).
Furthermore, many adapters exceed the maximum allowable capacitive
loading by as much as 50% thus further increasing the restore time.
Relying on a purely passive restore mechanism, one could not reduce
the arbitration cycle on a RS/6000 MCA server below 400ns.  This is a
significant overhead penalty for the IO bus when processor speed
approachs 50Mhz.  This disclosure describes...