Browse Prior Art Database

Personal Computer Comprehensive Testing for FastInitial Program Load

IP.com Disclosure Number: IPCOM000113281D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

DeBauche, B: AUTHOR [+4]

Abstract

Described is a software implementation for Personal Computers (PCs) to provide comprehensive testing for fast Initial Program Load (IPL) operations. The implementation provides a means of reducing Power-On Self Test (POST) time while maintaining overall system test coverage.

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This is the abbreviated version, containing approximately 52% of the total text.

Personal Computer Comprehensive Testing for FastInitial Program Load

      Described is a software implementation for Personal Computers
(PCs) to provide comprehensive testing for fast Initial Program Load
(IPL) operations.  The implementation provides a means of reducing
Power-On Self Test (POST) time while maintaining overall system test
coverage.

      In an effort to improve overall system availability, as used in
portable PCs, battery life and usability must be designed for rapid
initial operation.  In prior art, speed was achieved by curtailing,
or removing the system POST operations entirely.  In removing, or
curtailing POST, system integrity was compromised and if the system
developed a problem, the user would not be aware of it until the
failing part was used, or after damage was done to the user's data.
Maintaining system integrity and determining when the system has
problems are important requirements.  The concept described herein
provides a method of constructing a POST, while not degrading the
overall system integrity, while reducing POST operational time.

      The concept involves segmenting a robust system POST into
logical parts, or sections.  Each section is created such that it can
be executed alone to provide a part, but not all, of the power-on
test diagnostic coverage.  The intent of the partitioning is to allow
for a portion of the overall coverage to be executed during each fast
power-on cycle.  On subsequent power-on cycles, a different section
will be run with the sequence restarting when all sections have been
executed.  The partitioning of the test code and the method used to
provide continuity and program control between the power-on cycles
are described as follows:

      The POST is designed so that during a single power-on operation
of the system, only a small portion of the entire suite of tests,
called the Power-On Instance Test Suite (POITS), will be executed.
Each POITS is assigned a unique number, called the POITS ID, from 0
to n, where n is the maximum numb...