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Digital Data Separator with Jitter Testing

IP.com Disclosure Number: IPCOM000113289D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Armstrong, DR: AUTHOR

Abstract

Disclosed is a means of transforming self-clocking serial data, such as that used to transmit diskette Modified Frequency Modulation (MFM) data into separate clock and data signals while adjusting for bit jitter. This solution allows the developer to customize the circuit to satisfy specific requirements. One feature of this design would be to determine if the degree of jitter received on the incoming signal is at an acceptable level.

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This is the abbreviated version, containing approximately 90% of the total text.

Digital Data Separator with Jitter Testing

      Disclosed is a means of transforming self-clocking serial data,
such as that used to transmit diskette Modified Frequency Modulation
(MFM) data into separate clock and data signals while adjusting for
bit jitter.  This solution allows the developer to customize the
circuit to satisfy specific requirements.  One feature of this design
would be to determine if the degree of jitter received on the
incoming signal is at an acceptable level.

      The logic synchronizes a reference clock with the incoming
serial data to produce a self adjusting clock and corresponding data.
Depending on when the raw data is latched during the current clock
pulse, the following clock pulse will be shortened or lengthened in
order to better synchronize subsequent data pulses.

      The serial data pulse is latched by a reference clock that is a
multiple of the serial data rate.  This in turn latches the current
state of the counter which determines how late or early in the output
clock cycle the data pulse occurred relative to the previous pulse.
The next state is decoded from the latched state and is used to
determine the length of the following output clock pulse.  This
adjustment is necessary to center subsequent serial data pulses in
the transition window for better interpretation of the data that
follows.  Dataout is asserted during the next output clock pulse and
is used to clear the serial datain latch.

      For the p...