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Browse Prior Art Database

Balanced Local Bus Arbitration Method for Personal Computers

IP.com Disclosure Number: IPCOM000113291D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Combs, JL: AUTHOR

Abstract

Described is an architectural implementation, for Personal Computers (PCs) which utilize local bus communication functions, to provide balanced arbitration through the use of a balanced request/grant arbitration state machine.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

Balanced Local Bus Arbitration Method for Personal Computers

      Described is an architectural implementation, for Personal
Computers (PCs) which utilize local bus communication functions, to
provide balanced arbitration through the use of a balanced
request/grant arbitration state machine.

      The implementation provides an arbitration function, through
the use of algorithms, so that two local bus masters would receive
equal device priority to bus requests on an alternating priority
basis.  The last master would be denied bus access only if both
devices devices were requesting use of the bus.

      In PC local bus configurations when two devices are capable of
being a bus master, other than the Central Processing Unit (CPU), the
arbitration described herein will equally share the bus between the
two.  No higher priority is give to either of the two devices.  If
both devices are requesting the use of the bus, the last user would
be denied the bus and the other would be allowed use of the bus.  Any
device that used the bus often would become the least likely to use
the bus should both devices want access.  If only one device is
requesting the use of the bus, the two devices would be allowed use
of the bus and a flag would be set for future bus arbitration
purposes.

      Fig. 1 shows a block diagram of a balanced request/grant
arbitration state machine functions.  Fig. 2 shows a block diagram of
the various bus interconnections controlled by the...