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Programmable Logical to Physical Correlation in a Memory Map

IP.com Disclosure Number: IPCOM000113296D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Ash, KJ: AUTHOR [+4]

Abstract

Disclosed is a method to map logical addressing of a memory array to the physical addressing using a software programmable register array. The register array is used as a translation table from logical address range to physical bank select of the array.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Programmable Logical to Physical Correlation in a Memory Map

      Disclosed is a method to map logical addressing of a memory
array to the physical addressing using a software programmable
register array.  The register array is used as a translation table
from logical address range to physical bank select of the array.

      In the following table the register array for mapping logical
address to physical address is represented.  The three high order
address bits are decoded to select individual memory banks.  Each
bank select line has a register which contains the value of the high
order address bits which will activate the select.  The logical
address values assigned to each bank select are set by software.

      As can be seen in the table an encoded value of '000' will
result in the activation of 'Bank Select 4'.  In the same manner
'111' will result the activation of 'Bank Select 0'.