Browse Prior Art Database

Cache Line Operations Overlapped with Micro Channel Arbitration

IP.com Disclosure Number: IPCOM000113298D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

The technique of handling memory operations, to satisfy the DMA, described in this disclosure can increase the effective bus bandwidth of the Micro Channel*. This is achieved by overlapping the DMA cache line operations with the Micro Channel arbitration phase. This can be done for both Bus Master and DMA Slave operations.

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Cache Line Operations Overlapped with Micro Channel Arbitration

      The technique of handling memory operations, to satisfy the
DMA, described in this disclosure can increase the effective bus
bandwidth of the Micro Channel*.  This is achieved by overlapping the
DMA cache line operations with the Micro Channel arbitration phase.
This can be done for both Bus Master and DMA Slave operations.

      Most Micro Channel IOCC's (including the IO Channel Controller
on the Release 1 RS/6000) typically wait until all of the Bus Master
DMA and DMA Slave background operations are completed before
beginning the next Micro Channel arbitration sequence.  The
background operations will include all of the accesses required to
the memory subsystem to service the DMA in accordance with the
caching scheme chosen and any error detection and/or handling as
required by the system.  The following diagram, Fig. 1, illustrates
this typical DMA operation.

      The Release 2 RS/6000 machines contain a more sophisticated
IOCC (XIO) which significantly improves the Micro Channel performance
and bandwidth.  Unlike typical IOCC's, the XIO contains a robust
pipeline structure to alleviate channel bottlenecks and latencies.
In this type of structure, the IO bandwidth is limited primarily by
the Micro Channel Architecture rather than the implementation details
of the IOCC.  However, one area where the XIO implementation was able
to improve upon the perceived Micro Channel bandwidth lim...