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Browse Prior Art Database

Dual Level Clock Distribution Method

IP.com Disclosure Number: IPCOM000113311D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+4]

Abstract

Described is a hardware circuit implementation that provides two level clock regeneration for global and local distribution of clock phases in complex Very Large Scale Integration (VLSI) circuit chips while maintaining clock dead time and skew control.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dual Level Clock Distribution Method

      Described is a hardware circuit implementation that provides
two level clock regeneration for global and local distribution of
clock phases in complex Very Large Scale Integration (VLSI) circuit
chips while maintaining clock dead time and skew control.

      The dual level clock distribution method provides a means of
minimizing and controlling clock dead time and phase skew in multiple
phase and multiple frequency logical systems.  In addition, the
method is designed to reduce the need for custom design and layout
time in integrated circuit chips.  The concept consists of a
centralized clock generation system and a distribution network with
the local regeneration of the required clock phases at the logic
macros in the integrated chip.  The overall clock distribution
technique is to generate and control the required clock frequencies
and phases centrally at the clock module and to have a two level
clock regeneration for the global and local distribution of the clock
phases.

      Fig. 1 shows a block diagram of the overall clock distribution
network and Fig. 2 shows a schematic of the dual-phase clock buffer
circuitry.  The dual-phase clock buffer circuits are used both at the
central clock generation module and at the local regeneration module.
They maintain the appropriate clock dead time and skew control to
guarantee the functionality and integrity of the clock generation
system.  Several circuits can be used within a given functional macro
to control power dissipation at...