Browse Prior Art Database

Data-Gate-Decoder for 1Mx4bit Organized Dynamic Random Access Memories

IP.com Disclosure Number: IPCOM000113327D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Cordes, K: AUTHOR [+2]

Abstract

Disclosed is a logic decoder circuit that enables operation of 1Mx4bit organized Dynamic Random Access Memories (DRAMs) in an 4Mx1bit organized environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Data-Gate-Decoder for 1Mx4bit Organized Dynamic Random Access Memories

       Logic circuit of the data-gate-decoder

      Disclosed is a logic decoder circuit that enables operation of
1Mx4bit organized Dynamic Random Access Memories (DRAMs) in an
4Mx1bit organized environment.

      A 4Mx1bit organized DRAM requires 11 address bits for row and
column respectively.  In contrary to that, an 4Mbit DRAM, which is
1Mx4bit organized, only requires 10 address bits to select one
4bit-byte.  Additional data-gates all to select one of the 4bits of
the 4bit-byte by a data-gate-signal.

      Operating an 1Mx4bit organized DRAM in an 4Mx1bit organized
environment requires the generation of the data-gate-signal from the
11 address bits which are provided by the 4Mx1bit organized
environment.

      The invention relates to a data-gate-decoder as an 1 out of 4
logic which generates the data-gate-signal (DS 1-4) for the 1Mx4bit
organized DRAM from the highest row and column address (A10) of the
4Mx1bit organized environment.  The data-gate-decoder is realized
with commercial-available TTL-devices and offers therefore a small
size, high speed and low cost solution which is advantageous over a
programmable gate array (PGA) solution.  The logic circuit is shown
in the Figure.

      The data-gate-decoder can be used to realize 4Mx9bit Single
Inline Memory Modules (SIMMs) with 1Mx4bit organized DRAMs.