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Half/Full Speed Clocking of the 60X Interface from the System I/O Interface

IP.com Disclosure Number: IPCOM000113345D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Arimilli, B: AUTHOR [+3]

Abstract

The Graphics Input/Output (GIO) chip provides a subset of the IBM POWER PC Interface from the RS/6000 System I/O (SIO) interface for I/O device attachment to the RS/6000 processor. The SIO interface will run at the same rate or one-half the rate of the RS/6000 CPU and the GIO is clocked at the same rate as the SIO interface. Due to the high rates of speed of the CPU, the GIO has to be able to run the POWER PC interface at either the same speed or one-half the speed of the SIO interface while maintaining a synchronous relation between the two interfaces.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Half/Full Speed Clocking of the 60X Interface from the System I/O
Interface

      The Graphics Input/Output (GIO) chip provides a subset of the
IBM POWER PC Interface from the RS/6000 System I/O (SIO) interface
for I/O device attachment to the RS/6000 processor.  The SIO
interface will run at the same rate or one-half the rate of the
RS/6000 CPU and the GIO is clocked at the same rate as the SIO
interface.  Due to the high rates of speed of the CPU, the GIO has to
be able to run the POWER PC interface at either the same speed or
one-half the speed of the SIO interface while maintaining a
synchronous relation between the two interfaces.

      In order to run the POWER PC interface synchronously at the
same rate (full-speed) or at one-half the rate (half-speed) of the
SIO interface, a method was devised to allow the GIO to clock the
POWER PC interface only on cycles when both the SIO and POWER PC
interface clock.  A phase signal is generated such that in full speed
mode this signal is always active and in half speed mode this signal
is only active every other cycle.  This signal is then used to
select/deselect clocking of GIO boundary registers and latches and
also used to gate signals when brought in directly from the POWER PC
bus as required by POWER PC bus protocols, thereby causing the GIO
POWER PC interface to clock every SIO cycle when in full speed mode
and every other SIO cycle when in half speed mode.  The timing for
this signal relative to the SIO and POWER PC clocks in half speed
mode is shown in Fig. 1.

      Note that the phase signal must be generated so that it is
inactive during the time of the falling edge of the...