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Multimedia Digital Signal Processor Data Conversion Bus

IP.com Disclosure Number: IPCOM000113348D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 152K

Publishing Venue

IBM

Related People

Manson, PA: AUTHOR

Abstract

This Multimedia Digital Signal Processor Data Conversion Bus (CBUS) architecture has the following objectives:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Multimedia Digital Signal Processor Data Conversion Bus

      This Multimedia Digital Signal Processor Data Conversion Bus
(CBUS) architecture has the following objectives:

1.  Support multiple codecs on the same bus from one Mwave* DSP
    master.

2.  Allow codecs on the same bus to operate simultaneously at
    different sample rates.

3.  Support sample rates of up to 48 kHz.

4.  Allow devices other than codecs to attach to the bus (e.g., other
    multimedia peripherals).

5.  Allow dynamic identification of which device is active on the bus
    by any attached device.

6.  Require a minimum number of signal lines or pins to implement.

      CBUS is a Time-Division Multiplexed (TDM) serial bus with
clocking and framing controlled by a single master.  Up to four (4)
slave devices may be attached to the CBUS.  All devices are serviced
within a 48 kHz (20.833 uS) frame cycle.

      Each frame is organized as four 64-bit device slots.  A 64-bit
slot was chosen to allow the transmission or receipt of two L/R
channel 16-bit audio samples plus control information.  Each slave
device uses one device slot during each frame cycle to simultaneously
transmit and receive data from the master.  No restrictions are
placed on data formats within the device slot with the following
exception:

      If the attached device is a codec-type device operating with a
sample rate less than the 48 kHz frame cycle, the first bit of the DR
(transmitted from slave) device slot must be reserved as a data
update indicator (see operation below).  Likewise the last bit of the
same device slot transmitted from the master (DX) must also be
reserved as a data update bit.

The following bus signals are defined:

o   Data Transmit (DX)

          This signal is always sourced from the master, and is the
    serial transmit data from the master to each consecutive slave
    device.

o   Data Receive  (DR)

          This signal is sourced from each consecutive slave device
    during its assigned device slot within the frame cycle.  Slave
    devices must tri-state or receive-only this line unless their
    assigned device slot is currently being addressed.

o   Bit Clock (CLK)

          This bit synchronization clock is always sourced from the
    master at a rate of 48 kHz x 256 bits = 12.288 mHz.

o   Slot ID 0 (S0)

o   Slot ID 1 (S1)

          These slot ID signals are always sourced from the master
    and indicate which device slot is currently addressed.  The slot
    ID increments in gray code sequence (00, 01, 11, 10) and a
    delayed exclusive-or function can be used to generate a device
    slot synchronization signal from the slot ID (if required).

      The master always sources DX, CLK, S0, and S1.  The slot ID (S0
and S1) are incremented every 64 bits (64 cycles of CLK) to address
the next device slot.  During each device slot, both master and
...