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Functional Test Executing Actual Microprocessor Code

IP.com Disclosure Number: IPCOM000113351D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Bernbaum, NL: AUTHOR [+3]

Abstract

Very Large Scale Integration (VLSI) chips are burned in after manufacturing to reduce the early failure rate. Typical burn-in patterns for Level Sensitive Scan Design (LSSD) employ a portion of the LSSD scan test vectors, which usually provide good coverage of chip nets given the stiff constraint of limited burn-in machine vector memories (32k-64k). Integrated microprocessor / memory chip area, however, is more than 50% SRAM, which is not covered by LSSD patterns.

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Functional Test Executing Actual Microprocessor Code

      Very Large Scale Integration (VLSI) chips are burned in after
manufacturing to reduce the early failure rate.  Typical burn-in
patterns for Level Sensitive Scan Design (LSSD) employ a portion of
the LSSD scan test vectors, which usually provide good coverage of
chip nets given the stiff constraint of limited burn-in machine
vector memories (32k-64k).  Integrated microprocessor / memory chip
area, however, is more than 50% SRAM, which is not covered by LSSD
patterns.

      This problem is solved by employing a functional test executing
actual microprocessor code to provide improved burn-in coverage.

      This burn-in technique was developed for the MWave* Digital
Signal Processor (DSP) subsystem, which incorporates an IBM designed
digital signal processor, AT/ISA and Micro Channel* system bus
interfaces, 4K by 24 bits of instruction store RAM, 4K x 16 bits of
data store RAM, Musical Instruments Device Interface (MIDI), and
interfaces supporting a variety of audio bandwidth analog-to-digital
and digital-to-analog devices on a single integrated circuit, or
"chip."  This chip is currently implemented using level-sensitive
scan design (LSSD) latches in a vendor 0.8 micron double-metal layer
p-well CMOS circuit technology.  It is packaged in a 144 pin surface
mount plastic flat pack (PFP).

Description of the technique is as follows:

1.  The chip is put in LSSD test mode via test mode input pin level
    selection.  Machine language program for burn-in (hereafter
    referred to as "burn-in program") is loaded into on-chip memory
    via direct writing using address and data inputs which are
    multiplexed onto physical chip input/output pins in test mode.

2.  The chip is switched to normal functional mode via test mode
    input pin level selection.  Waveform(s) of appropriate frequency
    and duty cycle are applied to the chip oscillator input...