Browse Prior Art Database

Power-On Oscillator Control Circuit

IP.com Disclosure Number: IPCOM000113360D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 91K

Publishing Venue

IBM

Related People

Capps Jr, LB: AUTHOR [+6]

Abstract

Described is a hardware implementation to provide a power-on oscillator control circuit so as to improve Phase Lock Loop (PLL) initial power-on operations of computer systems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Power-On Oscillator Control Circuit

      Described is a hardware implementation to provide a power-on
oscillator control circuit so as to improve Phase Lock Loop (PLL)
initial power-on operations of computer systems.

      The power-on oscillator control circuit described herein
involves the use of the Intel P23-33/66* microprocessor and the
ability to reset to a known state during power-on operations.
Analysis indicated that the PLL circuitry in the microprocessor
required special attachment hardware for proper operation.  Prior art
required holding off the oscillator input to the microprocessor until
it reached proper operating voltage.  Several mechanisms were
proposed, including relays and zener diodes, but none would support
the worst case requirements and the reset specification.  Also,
previous solutions using the 50 MHz microprocessor did not require a
full operating voltage before the oscillator was enabled.
Consequently, the P24-33/66 could not be used in computer systems.

      The concept described herein for the P23-33/66 microprocessor
requires an absolute hold-off of the oscillator during the power-up
ramp, typically 20 to 30 milliseconds and a timing mechanism to
control the reset applied after the oscillator was enabled.  Because
the components in the system, including the oscillator, operate
erratically during power-on due to low voltage conditions, special
care is needed to force the required logic states.  The
implementation of the power-on oscillator control circuit is
sectioned into two parts: 1) delay of the oscillator output on
power-on and 2) control of the reset after the output is enabled.

      Fig. 1 shows a schematic of the power-on oscillator control
circuit.  The output of oscillator 10 is controlled through enable
pin 1, which is used primarily during manufacturing connected to a
pull-up resistor and output cable (not shown).  Resistor-Capacitor
(R-C) circuit 11 is connected to the input of logic gate 12.  To
guarantee that the oscillator enable output of logic gate 12, pin OEN
is forced low durin...