Browse Prior Art Database

Cache Storage Reliability Method for Personal Computers

IP.com Disclosure Number: IPCOM000113361D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 183K

Publishing Venue

IBM

Related People

Cerling, RD: AUTHOR [+3]

Abstract

Described is an architectural implementation to provide a method of increasing cache storage reliability of high speed microprocessors, as used in Personal Computers (PCs). The implementation utilizes a combination of features which check the validity of data, as processed through internal cache storage sections, of high speed microprocessors.

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Cache Storage Reliability Method for Personal Computers

      Described is an architectural implementation to provide a
method of increasing cache storage reliability of high speed
microprocessors, as used in Personal Computers (PCs).  The
implementation utilizes a combination of features which check the
validity of data, as processed through internal cache storage
sections, of high speed microprocessors.

      The combination of features used in the concept is such that
each feature is implemented for a specific reason.  A simple external
cache is used so that its construction has the reliability of main
storage protected by Error Correcting Code (ECC) and functions
through the microprocessor system.  Each major microprocessor
function is assigned its own integrated circuit, such as processor,
memory controller and cache controller.  The cache controller and the
memory controller both see the microprocessor storage request at the
same time.  The cache controller indicates if the data request is in
the cache and informs the memory controller to abort its storage if
the data is in the cache, often called a cache Hit.  When data is
available from the cache and tested for validity, the storage
controller has already aborted the cycle.  While the cache controller
could start a storage cycle itself, an excessive amount of special
circuitry would be required.  However, the concept uses the built-in
Back-Off operation so that the microprocessor can reliably restart
the storage request.  This allows the cache circuitry to be simple
and  forces a cache MISS indication on a restart storage request when
required.

      Typically, high speed microprocessors, such as the Intel 80486*
microprocessor, utilize high speed cache storage functions to store
frequently used areas of main storage.  When the main storage is
accessed, data can be copied into the high speed cache storage for
subsequent use.  However, the microprocessor's internal cache storage
may not provide checking for valid data.  As a result, invalid data
can cause un-seen data corruption, or even a system lock-up
condition.

      The concept provides methods which increase the cashe storage
reliability of high speed microprocessors.  Studies have shown that
certain storage media devices are subject to single bit failures,
often referred to as a Single Event Upset (SEU) failures.  A major
cause of a SEU is due to radiation and the frequency of the SEU is
often expressed as a probability of an SEU at a certain radiation
level.  Even at sea level, the background radiation level can cause
SEUs in storage systems.  As storage systems become very large, the
probability of a SEU affecting a system operation increases directly
with the size of the storage unit.  For example, a typical Intel
80386* microprocessor has approximately 3,700 data bits that are
subject to SEU's.  A bit of storage that is subject to SEU is then
said to be upsettable and the failure rate c...