Browse Prior Art Database

Method to Extend Personal Computer System Memory

IP.com Disclosure Number: IPCOM000113369D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Heinzmann, AS: AUTHOR [+5]

Abstract

Described is a hardware implementation to enable Personal Computers (PCs), such as the IBM PS/2 Models 90 and 95*, to extend its memory capability from 64 megabyte (MB) to 256 MB of system memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method to Extend Personal Computer System Memory

      Described is a hardware implementation to enable Personal
Computers (PCs), such as the IBM PS/2 Models 90 and 95*, to extend
its memory capability from 64 megabyte (MB) to 256 MB of system
memory.

      In prior art, PCs, such as the IBM Models 90 and 95, were
designed with a common planar board and a separate and upgradable
Central Electronics Complex (CEC).  The planar board contained the
memory socket positions and the CEC contained the memory logic.  The
common interface between the planar board and the CEC was limited to
ten memory address lines for supporting a maximum of 10 x 10
addressing positions.  This limited the Dynamic Random Access Memory
(DRAM) support to a one and four Mbit technology, which in turn
limited system support to 1/2/4 and 8 MB types memory modules.

      With the advent of 16 Mbit DRAMs, 16 and 32 MB memory modules
became available to enable the extension of system memory.  16 Mbit
DRAMs require either 11x11 or 12x10 addressing, while the common
interface supports only 10x10 addressing.  This restriction had the
effect of limiting PCs, such as the IBM PS/2 Models 90 and 95
systems, to supporting a maximum of 64 MB of planar memory, where
each planar supported up to eight memory modules.  By supporting
11x11 and 12x10 addressing, PCs, such as the Models 90 and 95, could
support up to 256 MBs of planar memory.

      The concept described herein is designed to extend the PC
system's memory capabilities by including 11x11 and 12x10 addressing.
It also includes a method of decoding from the memory controller,
multiplexing logic and a non-standard memory module pinout.  As a
result, the method will support 40 bit Error Checking and Correcting
(ECC) or 36 bit parity modules, utilizing 1 Mbit and 4 Mbit
technology DRAMS, or 39 bit ECC modules utilizing 16 M bit technology
DRAMS.

      The Figure shows the circuit configuration for the multiplexing
logic implementation to atta...