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Fully Tri-Stable On-Chip-Drive and On-Chip-Receiver with Active Termination

IP.com Disclosure Number: IPCOM000113372D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Walls, LA: AUTHOR

Abstract

The following describes a CMOS On-Chip-Receiver and Driver (OCR and OCD) with an active termination circuit and a method of utilizing the devices that are used in the receiver active termination to assist the driver. A dense circuit layout can be achieved because some of the circuit devices are shared between the OCD and OCR, and between the OCD and the active termination. The impedance of the active termination and the strength of the driver can be independently modified to match the circuit application. A significant improvement in receiver delay is realized because the on-chip signal is immediately echoed back to other circuits on chip. This is unlike other designs that connect the receiver at the output of the OCD.

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Fully Tri-Stable On-Chip-Drive and On-Chip-Receiver with Active Termination

      The following describes a CMOS On-Chip-Receiver and Driver (OCR
and OCD) with an active termination circuit and a method of utilizing
the devices that are used in the receiver active termination to
assist the driver.  A dense circuit layout can be achieved because
some of the circuit devices are shared between the OCD and OCR, and
between the OCD and the active termination.  The impedance of the
active termination and the strength of the driver can be
independently modified to match the circuit application.  A
significant improvement in receiver delay is realized because the
on-chip signal is immediately echoed back to other circuits on chip.
This is unlike other designs that connect the receiver at the output
of the OCD.  In addition, the circuit provides a way of putting the
driver output in a high impedance mode so it can be tested for
leakage during burn-in test or for bus communications between chips.

      A block diagram of the circuit is shown in Fig. 1 and the
complete circuit using FETs is shown in Fig 2.  How each of the FET
devices is used to form individual circuit element shown in the block
diagram is described in Fig. 2.  The OCD/OCR circuit is constructed
using a multiplexer, inverter, a non-inverting output buffer, an
inverting buffer and an inverting receiver stage.  The multiplexer is
used to select either an on-chip signal or an off-chip signal.
Output buffer 1 is the primary driver that is used to drive the
off-chip net.

      The two input multiplexer, inverter, tri-state inverter and
termination stage (buffer 2) form a bi-stable circuit when input 2,
the output of the OCD, is selected by the multiplexer.  The output
FET devices in buffer 2 act as termination devices when the circuit
is in receive mode.  The devices in buffer 2 are used to assist
buffer 1 as output drivers when the multiplexer input 1, the input
from on chip, is selected and the TERMINATION CONTROL enables the
drivers in buffer 2.  An INVERTING RECEIVER is used to supply the
correct polarity data to on-chip circuits.

      A truth table, given in Fig. 3, illustrates how the logical
inputs affect the circuit operation.  Shown in Fig 2 are two control
lines that are used in this design.  The OCD/OCR SELECT line is used
to change the function of the circuit from a driver to a receiver
circuit.  This line is also common to the multiplexer stage and
determines which input the multiplexer will select.  A high logical
state allows the multiplexer to selects the input from on-chip at the
OCD INPUT.  A logical low state allows the multiplexer to selects a
signal from off-chip at the OCD output.  A signal originating from
on-chip is routed...