Browse Prior Art Database

Frame Relay Congestion Control Mechanism

IP.com Disclosure Number: IPCOM000113381D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Lai, FY: AUTHOR [+3]

Abstract

Disclosed is a description of a mechanism that enables the Data Terminal Equipment (DTE) to slow down its transmission when congestion is detected in the Frame Relay network. This congestion control is done at the physical layer through an external Terminal Adapter (TA) and is totally transparent to the DTE.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Frame Relay Congestion Control Mechanism

      Disclosed is a description of a mechanism that enables the Data
Terminal Equipment (DTE) to slow down its transmission when
congestion is detected in the Frame Relay network.  This congestion
control is done at the physical layer through an external Terminal
Adapter (TA) and is totally transparent to the DTE.

This consists of two parts:

1.  Clock reduction mechanism

2.  Algorithm to determine the amount of rate reduction

There are two requirements for this clock reduction mechanism:

1.  Clock reduction is totally transparent to both the DTE and the
    network.

2.  The switching of the clock from one rate to another will not
    result in any data loss.

      The Figure shows a specific implementation using a 12 Mhz
master clock oscillator, and through the use of various clock
dividers, the following clock rates are generated: 2, 1.5, 1.2, 1,
0.85, 0.75, 0.6, 0.5, 0.38, 0.25 and 0.19 Mbps.  When TA decides to
reduce the clock rate, it issues a CHG=CLK command to the clock
selector.  The selector waits until all clocks are aligned, then
selects the clock that TA has requested.  This avoids any damage to
the data.

      Clock reduction mechanism by itself does not work because there
could be several Data Link Control Identifier (DLCI) multiplexing on
the same physical link, and when the clock rate is reduced, it
affects all the DLCIs on that specific link.  It will be unfair to
those DLCIs that are not congested but are sharing the same physical
link with the congested DLCI.  The objective of this algorithm is to
minimize this "unfairness".

1.  Each DLCI has a clock reduction rate associated with it, r(n),
    where n=1,...1023.  The rate can be adjusted based on the
    priorities, committed information rate (CIR), or types of
    services.  An extreme case is that there is only one clock
    reduction rate applied to all DLCIs.

2.  Let r(max) be the maximum clock reduction rate on a physical link
    over a measurement period.  It will be the summation of r(n)
    assuming all the DLCIs on this particular link have experienced
    congestion.  Frame Relay Standards have established a guide line
    that when DTE receives congestion notifications on a DLCI, the
    traffic for that specific DLCI be reduced by X%.  So let's equate
    r(max) to X.
         r(max) = maximum clock reduction rate on a physical link
                = Summation of all r(n) where n = 1,2,...1023
                = r(1) + r(2) + ...  + r(n)

          For  example,  if  X=25%, this means that the maximum clock
    reduction rates for  all  the  DLCIs  multiplexing  on  the  same
    physical  link within a time measured period is 25%.  This occurs
    when all the DLCIs that are multiplexing on the  same  link  have
    experienced congestion.

3.  Let  r(act) be the actual clock re...