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Power PC Interrupt Reset Operation Support in the RS/6000 System

IP.com Disclosure Number: IPCOM000113392D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+3]

Abstract

The Graphics Input/Output (GIO) chip provides a subset of the IBM Power PC Interface from the System I/O (SIO) interface for I/O device device attachement to the RS/6000* processor. In order to meet the Power PC interface interrupt handling requirements it is necessary for the GIO to perform a Power PC "interrupt reset operation" initiated from the RS/6000 processor via the SIO bus. The interrupt reset operation however is an address only transfer operation on the Power PC bus that is not supported by the SIO bus. Additionally the address for the interrupt reset operation is dependent on system interrupt parameters so it cannot be limited to an acceptably small address range.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 94% of the total text.

Power PC Interrupt Reset Operation Support in the RS/6000 System

      The Graphics Input/Output (GIO) chip provides a subset of the
IBM Power PC Interface from the System I/O (SIO) interface for I/O
device device attachement to the RS/6000* processor.  In order to
meet the Power PC interface interrupt handling requirements it is
necessary for the GIO to perform a Power PC "interrupt reset
operation" initiated from the RS/6000 processor via the SIO bus.  The
interrupt reset operation however is an address only transfer
operation on the Power PC bus that is not supported by the SIO bus.
Additionally the address for the interrupt reset operation is
dependent on system interrupt parameters so it cannot be limited to
an acceptably small address range.

      In order to provide a Power PC interrupt reset operation in the
RS/6000 system a single address (interrupt reset address -
x'FF00100C') in the register space of the GIO chip was defined which
when stored to by the processor causes the GIO chip to initiate a
Power PC interrupt reset operation with the Power PC bus address
equal to the data of the store from the processor.  Detection of the
interrupt reset address causes the GIO to assert the proper "address
only transfer type" on the Power PC interface with the data stored to
the interrupt reset address as the Power PC address.  This allows
software to build the interrupt reset address based on system
interrupt parameters and store it to a single address causing...