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Error Checking and Correction without Performance Loss

IP.com Disclosure Number: IPCOM000113396D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Barreh, J: AUTHOR [+2]

Abstract

DATA_IN | ------------ | REGISTER | ------------ | | | ------- | | ECC | | ------- | | | ------------ | | REGISTER | | ------------ | | ------- | MUX | ------- | TO REST OF RELOAD PIPE

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Error Checking and Correction without Performance Loss

     DATA_IN
            |
      ------------
      | REGISTER |
      ------------
           |     |
           |  -------
           |  | ECC |
           |  -------
           |     |
           |  ------------
           |  | REGISTER |
           |  ------------
           |    |
          -------
          | MUX |
          -------
             |
      TO REST OF RELOAD PIPE

      The Instruction Control Unit of the Power 2 processor was
required to add Error Check and Correct (ECC) logic to support
follow-on designs.  However, the timing constraints imposed by other
system components and the cycle time goals prevented the addition of
the ECC logic without lengthening the reload pipe by one cycle.  In
other words, the ECC would not fit within the timing constaints of
the pre-existing logic.

      While adding another cycle to the reload pipe (in essence,
giving the ECC logic its own cycle) would have solved the problem, it
would have also reduced performance.  The extra cycle increases the
amount of time between the time the ICU detects a need for data and
when that data is used by the ICU.

      The obvious solution for this problem is to introduce an extra
cycle for all reloads, thereby reducing system performance ev...