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Complementary Metal Oxide Semiconductor Differential Circuit with Inhibit

IP.com Disclosure Number: IPCOM000113410D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Dutta, S: AUTHOR [+2]

Abstract

A quality test (Idd test) of Complementary Metal Oxide Semiconductor (CMOS) chips requires circuits to demonstrate zero (0) current flow between Vdd (typically supply) and Vss (typically ground). This Idd test allows the quality monitoring of FET gate leakage current. Prior art of CMOS amplifier circuits implements this concept by inserting FETs in the path between Vdd and Vss. These inserted FETs cause performance degradation due to circuit delay, an offset to the common mode point and a reduced noise margin from a reduced input range.

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This is the abbreviated version, containing approximately 58% of the total text.

Complementary Metal Oxide Semiconductor Differential Circuit with
Inhibit

      A quality test (Idd test) of Complementary Metal Oxide
Semiconductor (CMOS) chips requires circuits to demonstrate zero (0)
current flow between Vdd (typically supply) and Vss (typically
ground).  This Idd test allows the quality monitoring of FET gate
leakage current.  Prior art of CMOS amplifier circuits implements
this concept by inserting FETs in the path between Vdd and Vss.
These inserted FETs cause performance degradation due to circuit
delay, an offset to the common mode point and a reduced noise margin
from a reduced input range.

      A common I/O configuration consists of off-chip
drivers/receivers combination.  It is widely used for BI-DI nets
application and for testability point of view, it is useful mode of
operation when this type of circuit is used.  This disclosure
proposes a CMOS differential circuit with inhibit mode for Rio Bravo
project.

      As shown in Fig. 1, when the driver is 'on' state, the receiver
has to be in an inhibit (disable) mode.  Both driver and receiver's
inhibit lines are controlled by A1 and A2 signals respectively.
Subsequently, when the receiver goes into "on' state, the driver has
to be in the inhibit stage by the signal A1.

      The proposed CMOS differential circuit with inhibit signal is
shown in Fig. 2.  The circuit is designed for mid-range reference
voltage.  The input signal and the reference voltage are used on the
g...