Browse Prior Art Database

Selectable Power-On Self-Test Modes

IP.com Disclosure Number: IPCOM000113417D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 111K

Publishing Venue

IBM

Related People

Cronk, D: AUTHOR [+7]

Abstract

Disclosed is a method providing a capability for a system to test itself during Power-On Self-Test (POST) in either a thorough and meticulous manner or a quick and expeditious manner.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Selectable Power-On Self-Test Modes

      Disclosed is a method providing a capability for a system to
test itself during Power-On Self-Test (POST) in either a thorough and
meticulous manner or a quick and expeditious manner.

      In a personal computer, the POST routine is responsible for
initializing and testing the hardware components of the system.
Additionally, data areas are set up and initialized by POST before
control is passed to the operating system.  While, in traditional
personal computer systems, POST initializes and thoroughly tests all
components, in recently-developed systems, increased levels of
technology and hardware have significantly increased the time
required for such thorough testing.

      Therefore, a personal computer system may be programmed to run
POST testing in either a Standard POST mode, in which the computer
system is initialized and thoroughly tested in the traditional way,
or in a Fast POST mode, in which the computer system is initialized
but minimally tested, reducing the time required to start the
operating system and application programs.  For example, the IBM
Personal System/2* Model 95 XP with 16MB of memory and 256KB optional
cache installed takes about two minutes to execute standard POST, but
only 35 seconds to execute fast POST.

      The user of a computer system having this feature selects the
POST execution mode through the Fast Startup Mode utility stored on
the system reference diskette, with this utility enabling or
disabling the Fast Start up mode.  The execution mode selected in
this way is stored in the Non-Volatile Random Access Memory (NVRAM)
of the system.

      Fig. 1 is a flow chart showing the process which occurs as POST
begins execution.  In block 10, NVRAM is tested to make a decision in
block 12 based on the validity of this code.  In block 14, if this
test has indicated that NVRAM is invalid, the default execution mode,
Standard POST, is forced; since if NVRAM is invalid, POST cannot
determine which mode has been selected.  Thus the standard POST mode
is executed in block 16.  On the other hand, if NVRAM is valid, the
POST mode selection information is read in block 18, and a decision
is based on this information in block 20.  If the Standard POST mode
has been selected, this mode is executed in block 16.  If the Fast
POST mode has been selected,...