Browse Prior Art Database

Microcode Trap Output for Development Debug of Integrated Circuit Control

IP.com Disclosure Number: IPCOM000113443D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 122K

Publishing Venue

IBM

Related People

Jaquette, GA: AUTHOR

Abstract

Disclosed is a circuit useful for debug of microcode which controls Integrated Circuits (IC) in a development environment. The circuit allows imaging of any bit in any register in the address space allowed by the attached chip selects. An elaboration of this concept to allow triggering on a combination of bits read from (or written to) any specified register is also disclosed. These circuits effectively allow instrumentation of bits inside contol or status registers, memory devices (such as RAM and ROM), or creation of a fictitious register bit to allow triggering on a specific event by writing to the bit imaged. This is useful for triggering oscilloscopes and logic analyzers on specific control states written by (or status states read by) the microprocesser.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Microcode Trap Output for Development Debug of Integrated Circuit
Control

      Disclosed is a circuit useful for debug of microcode which
controls Integrated Circuits (IC) in a development environment.  The
circuit allows imaging of any bit in any register in the address
space allowed by the attached chip selects.  An elaboration of this
concept to allow triggering on a combination of bits read from (or
written to) any specified register is also disclosed.  These circuits
effectively allow instrumentation of bits inside contol or status
registers, memory devices (such as RAM and ROM), or creation of a
fictitious register bit to allow triggering on a specific event by
writing to the bit imaged.  This is useful for triggering
oscilloscopes and logic analyzers on specific control states written
by (or status states read by) the microprocesser.

The following circuits can be integrated into any IC which is
attached to the microprocessor bus.

      Fig. 1 illustrates a simple implementation of the imaging
circuit for an Intel style microprocesser (could be easily modified
for some other style such as Motorola).  The address latch is
required for the Intel style microprocessor to capture the address on
the multiplexed address/data bus.  The register select decoding is to
allow writing of the two registers required to implement the imaging.
The top register is written with the address of the register to be
imaged.  The bottom register is written with the value indicating the
bit to be imaged within the register.  A data selector (multiplexer)
gates the selected bit on the data bus through to the D input of the
flip-flop.  A multiple bit digital comparator acts to compare the
address specified in the address register with the address presently
being addressed by the microprocesser.  If an address match occurs,
the output of the comparator strobes so as to latch the selected bit
present at the D input of the flip-flop to the output of the same.
The output of the flip-flop can be connected to an integrated circuit
output pin to allow imaging of the selected bit in the specified
register into instrumentation such as an oscilloscope.  Note that the
imaged bit could be specified to be anyware in the address space
allowed by the latched address bits and chips selects used in the
address comparator, even though no physical register exists within
the IC where the imaging circuit exists, thus imaging of register
bits or memory bits (RAM or ROM) ou...