Browse Prior Art Database

Delay Line Type Synthesizer

IP.com Disclosure Number: IPCOM000113459D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Iwata, K: AUTHOR [+2]

Abstract

Disclosed is a circuit for synthesizer which utilizes delay line function. By changing delay time of delay line, this synthesizer generates high frequency and high resolution clock.

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Delay Line Type Synthesizer

      Disclosed is a circuit for synthesizer which utilizes delay
line function.  By changing delay time of delay line, this
synthesizer generates high frequency and high resolution clock.

      The Figure shows the timing chart of synthesizer.  When start
signal goes 'High', synthesizer begins its generation.  The signal
which is delayed by DL1 is inverted by invertor and comes to DL1
again.  This repetition generates clock.  Generating frequency is
described following expression.
         f = 1 / (DL1 + Dand + Dinv)
         where : DL1 is delay time of programmable delay line
                 Dand is delay of and gate
                 Dinv is delay of invertor

      Dand and Dinv limits maximum frequency, but not affects
resolution.  Resolution is depends on delay time of programmable
delay line.  Therefore high resolution synthesizer is possible.

This theorem is applied to Phase Lock Loop function by used with
phase detector.