Browse Prior Art Database

Programmable Delay Line Control Signal Circuits

IP.com Disclosure Number: IPCOM000113463D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Balram, NN: AUTHOR [+2]

Abstract

Described is an architectural implementation to provide programmable delay line control signal circuitry for personal computers without sacrificing performance. The implementation includes seven programmable delay elements added to control signal paths. The delays enable gate arrays to meet required high speed timing specifications.

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Programmable Delay Line Control Signal Circuits

      Described is an architectural implementation to provide
programmable delay line control signal circuitry for personal
computers without sacrificing performance.  The implementation
includes seven programmable delay elements added to control signal
paths.  The delays enable gate arrays to meet required high speed
timing specifications.

      Typically, when gate arrays are designed and simulated, each
circuit has an estimated gate delay.  If the estimated gate delays
are different than the specified circuit parameters, high speed
circuits may not operate correctly due to variations in loading or
manufacturing processes.  In prior art, series resistors and/or logic
gates external to the gate arrays have been used to compensate for
the circuit operations.  Also, programmable delays have been used,
but typically involved full clock widths.

      Gate arrays that have access to Random Access Memory (RAM),
which is external to the gate array, must meet RAM timing
specifications.  In a gate array that is designed to write to a new
column in the RAM on every cycle, such as interleaved page mode
accesses, a control signal, a new column address, and new data are
launched to the RAM from the same clock edge.  As a result, it is
difficult to accurately predict, through simulation and timing
analysis, whether the valid address and data times at the RAM occur
prior to the control signal timing, as required by RAM timing
specifications.  However, the required setup time can be guaranteed
by delaying the signal path so as to allow oth...