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Mixed Voltage Complementary Metal Oxide Semiconductor Interface Circuit

IP.com Disclosure Number: IPCOM000113492D
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Cao, TA: AUTHOR [+4]

Abstract

Complementary Metal Oxide Semiconductor (CMOS) technology has been more and more attractive in terms of lower power supply requirement. The design is more challenging to make the circuit smaller and faster and of course less power consumption than ever. A mixed voltage interface circuit is needed when the chip input signal lines swing to a higher voltage than the chip power supply.

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Mixed  Voltage Complementary Metal Oxide Semiconductor Interface
Circuit

      Complementary Metal Oxide Semiconductor (CMOS) technology has
been more and more attractive in terms of lower power supply
requirement.  The design is more challenging to make the circuit
smaller and faster and of course less power consumption than ever.  A
mixed voltage interface circuit is needed when the chip input signal
lines swing to a higher voltage than the chip power supply.

      In the current CMOS project, there is a requirement such that a
chip with a 2.5V power supply has to receive 3.3V signal lines from
another chip.  With .8V higher than what the chip should operate at,
this voltage can cause the break/down of devices on the chip.  To
solve this problem: a circuit has been designed to bring down the
level of 3.3V to 2.5V so the chip can operate.

      Basically, the interface circuit goes with an OCR (off chip
receiver) and the OCR receives signal lines which come from an OCD
(off chip driver) on another chip.  This interface circuit is in
front of the OCR and converts the signal to the right voltage level.

      As industry standard requirement, the VOH and VOL of a 3.3V OCD
and VIH and VIL 2.5V OCR are shown in Fig. 1.  By applying this, a
circuit can be designed to satisfy the requirement to convert from
3.3V to 2.5V.

      The detail circuit diagram is shown in Fig. 2.  In this
diagram, the incomming signal is at 3.3V and there is a N-device (Q...