Synchronization of Multi-Media Digital Signal Processor with Integrated Services Digital Network Timing
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Bass, BH: AUTHOR [+3]
A method for synchronization of a Digital Signal Processor (DSP) with Integrated Services Digital Network (ISDN) network timing is disclosed. Synchronization of peripheral clocking and interrupt generation is accomplished in order to maintain compatibility with existing software tasks ported from other environments.
Synchronization of Multi-Media Digital Signal Processor
Services Digital Network Timing
A method for
synchronization of a Digital Signal Processor
(DSP) with Integrated Services Digital Network (ISDN) network timing
is disclosed. Synchronization of peripheral clocking and interrupt
generation is accomplished in order to maintain compatibility with
existing software tasks ported from other environments.
DSP supports multimedia environments which include
telephony, audio, and video processing. A multi-tasking operating
system makes it possible to have multiple such tasks active
concurrently. This DSP has integrated peripheral interfaces for
analog CODEC (Digital-to-Analog and Analog-to-Digital converters).
This peripheral circuitry requires a high-frequency local oscillator
in order to generate all of the required timing for the interface.
In order to satisfy all of the timing requirements of the Mwave
subsystem, this oscillator frequency must be 23.04 MHz.
WaveRunner** ISDN adapters use the Mwave DSP with interface
circuitry added for the ISDN connection. Since the ISDN network
requires each device connecting to it to synchronize to network
timing, data coming through that ISDN connection would not be
synchronous to the 23.04 MHz Oscillator frequency required to support
the DSP peripheral interfaces. The implication of this lack of
synchronization is that the DSP would have to process a variable
amount of data each time it was interrupted, requiring extra code to
figure out how much data to process each time. Additional MIPS would
have to be reserved to handle this extra workload. In fact, since
the workload would be inconsistent, the system would require that
MIPS be reserved which would not always be used, resulting in an
additional reduction of available MIPS. Some tasks require sample
rate conversion from 8 KHz to 9.6 KHz. If the processes at these two
frequencies are synchronous, a relatively simple
interpolator/decimator task can provide the required rate conversion.
However, in the case where the two processes are not synchronous, a
much more complicated asynchronous interpolator is required (along
with additional MIPS to implement it).
the DSP was not sensitive to an irregular duty
cycle on the Master Oscillator, but was only dependent on the average
frequency of the pulses, an all-digital pulse gating circuit was
implemented to generate the 23.04 MHz clock from a higher frequency
(33 MHz) clock used to drive the DSP processor.