Browse Prior Art Database

Power/PowerPC Binary Incompatibility Analyzer

IP.com Disclosure Number: IPCOM000113546D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Heisch, RR: AUTHOR

Abstract

The PowerPC* architecture is a derivative of the Power architecture and, for the most part, provides binary compatibility for programs originally written and compiled (or assembled) for Power platforms. However, there are several deviations from the Power architecture which may result in incompatibilities or performance problems. In particular, 34 Power architecture instructions have been deleted from the PowerPC architecture (5 for the PowerPC601). Also, there are 23 classes of functional deviations or incompatibilities ranging from the use of reserved bits and previously/newly privileged instructions to the use of special purpose registers (including the real-time clock registers) and instruction/data cache manipulation instructions.

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Power/PowerPC Binary Incompatibility Analyzer

      The PowerPC* architecture is a derivative of the Power
architecture and, for the most part, provides binary compatibility
for programs originally written and compiled (or assembled) for Power
platforms.  However, there are several deviations from the Power
architecture which may result in incompatibilities or performance
problems.  In particular, 34 Power architecture instructions have
been deleted from the PowerPC architecture (5 for the PowerPC601).
Also, there are 23 classes of functional deviations or
incompatibilities ranging from the use of reserved bits and
previously/newly privileged instructions to the use of special
purpose registers (including the real-time clock registers) and
instruction/data cache manipulation instructions.

      A level of binary compatibility will be achieved by emulating
deleted instructions (and perhaps a subset of the incompatible
instructions) in the kernel using the illegal instruction trap.
However, kernel emulation does suffer a potentially severe
performance disadvantage.  Emulation will require anywhere from 100
to 1000 CPU cycles (400 cycles measured for the 601) per deleted
instruction due to context switch overhead which can easily result,
depending upon deleted instruction utilization, in severe performance
degradations.  Incompatible instructions which do not cause the
illegal instruction trap will not be emulated and can potentially
alter the expected behavior of a program.

      This disclosure presents a method for statically analyzing an
existing Power binary to detect potential performance and
incompatibility problems if and when the same binary is executed on a
PowerPC platform.  This method has been implemented and will be
shipped to customers as the (tentatively named) Power Binary Analyzer
(PBA) tool.

      The general idea is to scan the text section of an existing
AIX* program and to flag all occurrences of either deleted or
incompatible instructions.  While this approach does not indicate
dynamic instruction utilization, it will at least indicate the
potential for problems (it does, however,...