Browse Prior Art Database

Multi-Mode Level-Sensitive Scan Design-Compliant Edge-Sensing Latch

IP.com Disclosure Number: IPCOM000113557D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 141K

Publishing Venue

IBM

Related People

Noll, MG: AUTHOR [+3]

Abstract

Disclosed is a Multimode-Edge-Sensing Latch (MESL) which is capable of several modes of operation including: asynchronous edge-sensing with synchronous set/reset modes, asynchronous edge-sensing with asynchronous set/reset modes, and full Level-Sensitive Scan Design (LSSD) operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multi-Mode Level-Sensitive Scan Design-Compliant Edge-Sensing Latch

      Disclosed is a Multimode-Edge-Sensing Latch (MESL) which is
capable of several  modes of operation including:  asynchronous
edge-sensing with synchronous set/reset modes, asynchronous
edge-sensing with asynchronous set/reset modes, and full
Level-Sensitive Scan Design (LSSD) operation.

      Fig. 1 shows the complete MESL implementation.  Note that all
incoming signals to the MESL assert with active high polarity.
During functional operation with a synchronous set/reset,
LSSD_C_CLK_1, LSSD_C_CLK_2, POSITIVE_SCAN_GATE and NEGATIVE_
SCAN_GATE assume high polarity levels.  Consequently, not all
elements shown in Fig. 1 activate during these modes.  The cone of
logic composed of elements D3, D7, D8, D10 and D15, which generates
the polarity to be latched, ensures set-request dominance over both
reset-requests and incoming data; it also ensures dominance of
reset-requests over incoming data, in the absense of an asserted
set-request.  When sensing asynchronous incoming edges, polarities
are stored in D19's L1-half by edge-derived leading pulses of
phase-separated pairs generated by splitter D1 (Fig. 2).  Leading
pulse deassertion is coincident with rising edge arrival.
Consequently, incoming data is captured on a rising edge; this
constitutes rising edge sensitivity.  Polarities are transferred from
D19's L1 to D19's L2 by trailing pulses of phase-separated pairs
generated by splitter D1.  Device D9 provides edge-derived trailing
pulses to the L2-system-port's C2 clock input.

      When synchronously setting or resetting the latch, polarities
are stored in D19's L1-half by leading pulses of phase-separated
pairs, generated from the main functional clock within external
logic.  Multiplexer D16 selects the clock source for L1-system-port's
C1 clock, based on set/reset assertion, as signaled by D2.  Set/reset
polarities are transferred from L1 to L2 (of D19) by trailing pulses
dervied from the main functional clock.  Derive D18 supplies trailing
pulses, externally derived from functional clock, to the
L2-scan-port's B clock input.

      During functional operation with asynchronous set/reset,
additional lines become static.  FUNCTIONAL_C_CLK AND
FUNCTIONAL_B_CLK assume high polarity values.  In these modes,
asynchronous edge-sensing behaves identically and dominance relations
within data sourcing remain unchanged.  Latch setting and resetting
no longer occur in coincidence with events in external logic, though,
because there is no longer reliance on main functional clocking.
Set/reset intervals last as long as set/reset assertion, as signaled
by D2; during this period data flushes through D19's L1 and L2
halves.  Data is latched at the falling edge o...