Browse Prior Art Database

Add-On CPU Board

IP.com Disclosure Number: IPCOM000113570D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Oba, N: AUTHOR [+3]

Abstract

This article describes an add-on CPU board, which is a field-replaceable CPU board containing a new CPU and a second-level cache memory. It is used to boost the system performance by replacing the original CPU. The mechanism disclosed in this article provides the bus handshakes that are fully compatible with Intel i486* and its families in terms of standard CPU accesses and system snooping.

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Add-On CPU Board

      This article describes an add-on CPU board, which is a
field-replaceable CPU board containing a new CPU and a second-level
cache memory.  It is used to boost the system performance by
replacing the original CPU.  The mechanism disclosed in this article
provides the bus handshakes that are fully compatible with Intel
i486* and its families in terms of standard CPU accesses and system
snooping.

      The add-on CPU board consists of a CPU, a second-level cache
memory, and an ADS logic, as shown in Fig. 1.  The role of the ADS
logic is to control ADS# in accordance with the CPU accesses and
system snooping.  If the current CPU access is served by the system,
the ADS logic generates DADS#.  If the current CPU access is served
by the add-on CPU board, on the other hand, the ADS logic does not
generate DADS#.
  1) Cycles that are served by the system.  I/O, special, and
non-cacheable memory cycles are served by the system.  When the cache
memories employ the write-through policy, all the write cycles are
also served by the system.  The ADS# logic generates DADS# in
response to the CPU ADS#, as shown in Fig. 2.
  2) Cycles that are served by the add-on CPU board.  The
cacheable memory cycles that hit in the second-level cache memory are
served by the add-on CPU board.  A cache hit or miss is determined by
looking up the tag memory of the second-level cache memory.  If a
cache hit is detected, the cycle is served by the second-level cach...