Browse Prior Art Database

External Post Write Buffer Protocol for Personal Computers

IP.com Disclosure Number: IPCOM000113575D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 198K

Publishing Venue

IBM

Related People

Haig, RB: AUTHOR [+2]

Abstract

Described is a an architectural implementation to provide a simple protocol for an external posted write buffer, as used in Personal Computers (PCs). The purpose of the external post write buffer protocol is to attain high performance between a processor, or local bus master, and the memory controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

External Post Write Buffer Protocol for Personal Computers

      Described is a an architectural implementation to provide a
simple protocol for an external posted write buffer, as used in
Personal Computers (PCs).  The purpose of the external post write
buffer protocol is to attain high performance between a processor, or
local bus master, and the memory controller.

      Typically, in order to obtain high performance between the
processor, or local bus master, and the memory controller, a protocol
is required to be able to post writes to memory.  By posting the
writes, the bus master device can continue to the next operation.  In
order to post writes, the data to memory must be held until the
memory has been accessed correctly.  This requires either data to be
brought through the module, or an external device must hold the data.
The concept described herein provides a simple protocol in the form
of an external posted write buffer so as to attain the higher
performance required.

      In prior art, the most common way of creating a posted write
buffer was to bring the data into the memory controller and then to
send the data out through the memory controller.  This created the
need for two full buses and the need for large pin packages.  A
second method was to create an external posted write buffer, but to
create a state machine inside the module to control the posting of
the writes.  This state machine required a large number of pins and a
complex set of logic.

      The concept described herein reduces the pin requirements and
the complexity of the posted write buffer logic by creating a
protocol that quickly informs the external posted write buffer when
to latch the data.  The technique creates an external posted write
buffer that uses fewer pins and simple logic.  The prior art concept
did not provide an acceptable protocol for creating an external
posted write buffer due to the increased packaging and logic
requirements.

      The external posted write buffer protocol implementation uses
only three pins from the memory controller to signal the external
posted write buffer when to latch the data and to signal when the
data should be driven from the memory bus.  The protocol allows the
external posted write buffer to be used for posting write data and
for driving the data from the memory bus to the local bus.  Also, the
protocol does not require additional wait states which would degrade
the system.

      The external posted write buffer protocol between the memory
controller and the posted write buffer consists of three signals:
MDTR; MDEN; and MDHD.

      The MDTR signal informs the posted write buffer module of the
direction data is flowing.  The MDEN signal informs the posted write
buffer of when the cycle is valid.  This allows the posted write
buffer to know when to drive, or receive, data to the memory bus and
the local bus.  The MDHD signal is used to inform the posted write
buffer...