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System Post Test for Central Processing Unit Power Plane

IP.com Disclosure Number: IPCOM000113599D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Hanson, G: AUTHOR

Abstract

Disclosed is the application of a power management suspend and resume architecture of a portable system, during Power-On Self Test (POST), so that the code associated with this test can verify that power to the processor Central Processing Unit (CPU) can be removed as required, and that power can be restored to the processor upon the detection of a hardware interrupt. This process notifies the user if an error occurs in testing the performance of these functions.

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This is the abbreviated version, containing approximately 52% of the total text.

System Post Test for Central Processing Unit Power Plane

      Disclosed is the application of a power management suspend and
resume architecture of a portable system, during Power-On Self Test
(POST), so that the code associated with this test can verify that
power to the processor Central Processing Unit (CPU) can be removed
as required, and that power can be restored to the processor upon the
detection of a hardware interrupt.  This process notifies the user if
an error occurs in testing the performance of these functions.

      The suspend and resume functions are used to extend the useful
charge of the system battery without causing a disruption of system
operation that would be noticeable to the user.  For example, the
suspend and resume functions described in [*]  allow the operating
system to initiate the removal and restoration of CPU power in a
manner that is virtually transparent to the user.  Since the removal
of power to the CPU affects only the CPU, the power to other systems,
such as the display, memory, and I/O circuits, is unchanged.

      The basic problem in verifying the removal and restoration of
CPU power is that the normal flow of code is disrupted by the removal
of power.  When the power is subsequently restored, various memory
pointers contained in the CPU registers just before the power loss
are now reset to entirely different locations, losing the original
code path.

      While the suspend and resume architecture described in (*) has
been developed to allow re-entry to system operational code, the use
of that architecture in the POST testing process employs POST code as
the final endpoint.  Therefore, only a small subset of the suspend
and resume architecture is used.

      This particular test procedure begins when CPU_OFF, the portion
of POST test verifying this function, sets the Real-Time Clock (RTC)
to provide periodic interrupts.  Next, CPU_OFF stores the...