Browse Prior Art Database

Determination of Excessive Single-Bit Errors

IP.com Disclosure Number: IPCOM000113612D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 119K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+3]

Abstract

Disclosed is a comprehensive method for handling excessive single-bit errors occurring as a SIMM memory bank is accessed. With this method, single bit errors occurring in each SIMM bank are continuously monitored, as the number of such errors is normalized to the number of accesses of the SIMM bank, creating an error frequency distribution over time. If the frequency of errors is greater than a threshold value, an Non-Maskable Interrupt (NMI) is issued, alerting the operating system of excessive single-bit errors. A mechanism is also provided for tracking the cause of excessive errors to an individual SIMM bank.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Determination of Excessive Single-Bit Errors

      Disclosed is a comprehensive method for handling excessive
single-bit errors occurring as a SIMM memory bank is accessed.  With
this method, single bit errors occurring in each SIMM bank are
continuously monitored, as the number of such errors is normalized to
the number of accesses of the SIMM bank, creating an error frequency
distribution over time.  If the frequency of errors is greater than a
threshold value, an Non-Maskable Interrupt (NMI) is issued, alerting
the operating system of excessive single-bit errors.  A mechanism is
also provided for tracking the cause of excessive errors to an
individual SIMM bank.

      Fig. 1 is a schematic diagram of the logic used to provide this
feature.  An access counter 10 and a single-bit error counter 12 is
provided for each SIMM bank (not shown).  A threshold register 14
provides a predetermined threshold level which is compared, in a
comparator 16, with the output of each single-bit error counter 12.
The outputs of comparators 16 are provided as inputs to gates 17.  A
control register 18, providing additional inputs to gates 17,
determines the SIMM banks for which this feature is enabled.  The
output lines of gates 17 are provided as inputs to a status register
20, which in turn provides an input to an NMI handler 22 whenever one
of the SIMM banks for which this feature is enabled has been
determined to have excessive single-bit errors.

      Fig. 2 is a schematic diagram of an access counter 10, which is
configured as an 8-bit counter register incrementing with every
fourth access to the SIMM bank with which the counter 10 is
associated.  After 1024 such accesses, counter 10 resets to zero and
provides a reset signal RESET_X, with X indicating the number of the
associated SIMM bank.

      Fig. 3 is a schematic diagram of a single-bit error register
12, which is configured as an 8-bit counter register incrementing
with every single bit error detected at an associated SIMM bank by
conventional means (not shown).  This register 12 is reset by the
RESET_X signal from the access counter 10 to which it is connected.
Thus, each register 12 counts up to the number of single-bit errors
occurring during an interval in which 1024 accesses are made to the
associated SIMM bank.  This arrangement provides for counting up to
256 single-bit errors.

      Fig. 4 is a schematic diagram of threshold register 14, which
is configured as an 8-bit register programmed to store the maximum
number of single-bit errors, up to 256, determined to be allowable
during an interval in which 1024 accesses occur.  The output of each
single-bit error...