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Clock-Controlled Power Save Method

IP.com Disclosure Number: IPCOM000113619D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Kubo, H: AUTHOR [+2]

Abstract

A clock controlled power save method is described to reduce the power consumption of a microprocessor without any large scale circuit like the power management microprocessor. The microprocessor sets its clock speed as high, middle, or low by itself, depending on the amount of transactions which the whole system needs.

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Clock-Controlled Power Save Method

      A clock controlled power save method is described to reduce the
power consumption of a microprocessor without any large scale circuit
like the power management microprocessor.  The microprocessor sets
its clock speed as high, middle, or low by itself, depending on the
amount of transactions which the whole system needs.

      The Figure shows an implementation of the method.  The
oscillator supplies N Hz clock to the clock generator which generates
(N/2) Hz and (N/4) Hz clocks.  The microprocessor estimates the
amount of transactions, then sets the clock speed (N Hz, (N/2) Hz, or
(N/4) Hz) in the clock control register.  The clock selector selects
one of the three clocks according to the clock control register and
supplies it to the microprocessor.

      In this way, the average power consumption of the
microprocessor is re- duced with small circuit.