Browse Prior Art Database

Interconnect Verification Method for Boards

IP.com Disclosure Number: IPCOM000113625D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 261K

Publishing Venue

IBM

Related People

Dombrowski, C: AUTHOR [+6]

Abstract

Disclosed is a method for verifying interconnections to the planar (system) board of an IBM PS/2* System to ensure that signal connections made through the planar board are verifiable before the signals are used, and that such signals can be captured in the event of an operational error. This method provides error detection and isolation between the planar board and the processor complex card. The extension of the verification process to further determine which component caused a failure is also disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 22% of the total text.

Interconnect Verification Method for Boards

      Disclosed is a method for verifying interconnections to the
planar (system) board of an IBM PS/2* System to ensure that signal
connections made through the planar board are verifiable before the
signals are used, and that such signals can be captured in the event
of an operational error.  This method provides error detection and
isolation between the planar board and the processor complex card.
The extension of the verification process to further determine which
component caused a failure is also disclosed.

      The planar boards used by systems such as the IBM Models 90 and
95 have become mainly interconnect vehicles for Micro Channel* I/O
functions, since the processor and it associated functions have been
moved off the planar board to a separate processor card.  This
separation may cause several error conditions that cannot exist when
the processor is resident on the planar board.  For example, if a
critical VLSI pin in the planar board assembly breaks contact so that
it can no longer communicate with the processor card through the
processor card interface, the processor cannot determine which side
of the interface is bad, not having, in fact, determined that the
interface is good.

      This interconnect verification method relies on the ability of
the processor card, as an intelligent FRU, to vary a set of signals
which traverse the interface, such as the bus signals, and to sample
the variations on a different set of signals also traversing the
interface.  The non-intelligent FRU, in this case the planar board,
receives the signals being varied by the processor card, "wrapping"
them on the signal lines being sampled by the processor card.  The
wrap  is performed with a latching register having inputs distinct
from its outputs.  The wrap is controlled by the intelligent FRU,
since its circuitry can be verified before the wrap is initiated.
Once the signals are verified across the interface, they may be used
by the non-intelligent FRU for communication, with any subsequently
occurring errors being attributed to the non-intelligent FRU, since
the intelligent FRU and the interface have both been determined to be
valid.

      The intent in implementing this method is to provide
interconnect verification for all Micro Channel signals.  For
example, for certain planar boards, the following signal nets are
verified---address (0:31); data (0:31); byte enables -BE(0:3), byte
high enable -SBHE, card size 16/32 return - DS_16RTN, -DS_32RTN; data
parity enable -DPAREN; and data parity +DPAR(0:3).  The address and
data buses are checked first, since they can then be used for
verifying the remaining signals.  Using the +ISOLATE_LOCAL_MASTER,
-PROC_CS_16 & -PROC_CS_32, +M/-IO, S(0) & S(1), -CMD, and -ADL
signals for latching and read-back verification provides an
indication that these signals are also connected from the processor
to the planar.  Expected extensions to thi...