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Timing Analyzer for Circuits having Level Sensitive Latches

IP.com Disclosure Number: IPCOM000113631D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Batarekh, C: AUTHOR

Abstract

A method is described for incrementally computing and updating timing values in an environment, e.g., synthesis, in which the underlying model structure is subject to change. The method is general in that it can handle circuits with and without level sensitive latches, i.e., circuits having a timing graph containing cycles. Minimal recomputation is required to reply to a timing query. Cycles are detected that cannot be timed statically.

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Timing Analyzer for Circuits having Level Sensitive Latches

      A method is described for incrementally computing and updating
timing values in an environment, e.g., synthesis, in which the
underlying model structure is subject to change.  The method is
general in that it can handle circuits with and without level
sensitive latches, i.e., circuits having a timing graph containing
cycles.  Minimal recomputation is required to reply to a timing
query.  Cycles are detected that cannot be timed statically.

      Basically, the method is comprised of a bookkeeping mechanism
in which timing variables, e.g., arrival, required, slew, and delay
times, are categorized in one of three states: 1) valid and changed,
2) valid and not changed, and 3) invalid.  Those variables in states
1 and 2 do not have to be recomputed.  Those variables in state 3
have to be recomputed only if dependent values have changed.  When a
timing variable changes due to a structural change to the model, all
timing variables dependent upon that variable are invalidated.
Recomputation is thus minimized by placing all invalid timing
variables in category 3.

      Because the method is general, it can handle circuits with and
without level sensitive latches.  A circuit timing graph need not be
acyclical (or levelizable).  A depth first traversal is used
regardless of the timing graph topology.  If this traversal detects a
cycle, an additional step is called to propagate the timing values
a...