Browse Prior Art Database

Automatic Regulation of Processor Frequency for Personal Computers

IP.com Disclosure Number: IPCOM000113634D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 136K

Publishing Venue

IBM

Related People

Abrahamsen, R: AUTHOR [+3]

Abstract

Described is an architectural implementation to automatically regulate the frequency of the processor, as used in Personal Computers (PCs), in accordance with the speed of circuits affected by the environment. The technique utilizes a programmable voltage controlled ring oscillator to provide fractional clocking outputs.

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Automatic Regulation of Processor Frequency for Personal Computers

      Described is an architectural implementation to automatically
regulate the frequency of the processor, as used in Personal
Computers (PCs), in accordance with the speed of circuits affected by
the environment.  The technique utilizes a programmable voltage
controlled ring oscillator to provide fractional clocking outputs.

      Typically, the clocks in microprocessors, as used in PCs, are
being operated at increasingly faster frequencies which in turn can
result in transmission line quality problems.  Generally the
processor is interfaced with several off-chip buses which are clocked
at fixed frequencies.  The processor often is equipped with a clock
doubler, tripler, quad, etc., time of day function and a power
management operation which entails stopping the clock.  All of these
operations must be accomplished so as to provide maximum possible
performance.

      Fig. 1 shows a timing chart of a normalized frequency of a
typical processor, which over the life of the program being run will
exhibit a performance distribution that will range from 25 MHz to 50
MHz.  This wide range requires processor sorting so as to
differentiate the operation of the processor and to maximize the
return on the manufacturer's design.  The sorting, by the processor
manufacturer, results in two product operational distributions, such
as 25 MHz and 37 MHz.  The sorting is done at worst case power supply
and temperature extremes so that the performance of the processor can
be determined by this sort.

      Fig. 2 shows a block diagram of a typical processor.  The
various functions require the clock, within the processor, to operate
as fast as possible.

      Fig. 3 shows a block diagram of the fixed clocking section and
the performance clocking section.  There are several areas of fixed
clock interfaces, such as a feature bus, memory, and time-of-day.
Also, there are variable clock areas, such as the processor, floating
point processor, the working registers, and the level 1 cache.  This
combination is variable because it is sorted at final module test and
is combined to work at worst case frequency.  This frequency is
provided by an off chip clock input at the correct frequency for that
speed sort.  One prior art innovation uses an off-chip clock signal
to provide an on-chip clock distribution of a 1X, 2X, 3X, etc.
frequency distribution.  Processor versions have power controls for
the clock so that the clock can be slowed down, or even stopped.  It
is important to note that the data integrity is to be maintained
between the two major areas of static clocking and variable clocking
so that data is transferred across the boundary between the fixed
frequency parts and the variable parts, as shown in the...