Browse Prior Art Database

Automatic Program for Loading Data Transfer for Personal Computers

IP.com Disclosure Number: IPCOM000113637D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Cook, DC: AUTHOR [+5]

Abstract

Described is a logic implementation to provide automatic program loading of data transfer information for the Small Computer System Interface (SCSI) bus, as used in Personal Computers (PCs), to increase operational performance.

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Automatic Program for Loading Data Transfer for Personal Computers

      Described is a logic implementation to provide automatic
program loading of data transfer information for the Small Computer
System Interface (SCSI) bus, as used in Personal Computers (PCs), to
increase operational performance.

      In prior art, the SCSI controller would complete a message, or
command, phase and wait for the microprocessor to service the
interrupt.  Then the microprocessor would program all of the
registers necessary to start the data transfer process.

      The concept described herein provides a means of improving the
operational performance on the SCSI bus by reducing the
microprocessor latency whereby data information is loaded for the
next nexus while the current nexus is still active.  In this way, the
SCSI bus is made more efficient by allowing the information for the
next transfer to be programmed into background registers.  The
registers are arbitration, selection and re-selection (ASR) registers
and are used while the current SCSI transfer is still active.

      In order to eliminate confusion, the background register names
are identified as: ASR Data Transfer Count; ASR Data Control; and ASR
Local Bus Control Registers.  This ASR designator serves to remind
the user that these registers must be programmed at the same time as
the ASR state machine message and command registers are programmed.

      In actual operation, data in the background regi...