Browse Prior Art Database

Generalized Interrupt Routing Mask for Global Queues

IP.com Disclosure Number: IPCOM000113643D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 165K

Publishing Venue

IBM

Related People

Arndt, RL: AUTHOR [+2]

Abstract

Disclosed is a hardware/software interface that allows software to enable and inhibit interrupts from being sent to specific processors in an Symmetric Multi-Processor (SMP) System from Global Queues. Define this for a wide variety of hardware system implementations, including multibus structures.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

Generalized Interrupt Routing Mask for Global Queues

      Disclosed is a hardware/software interface that allows software
to enable and inhibit interrupts from being sent to specific
processors in an Symmetric Multi-Processor (SMP) System from Global
Queues.  Define this for a wide variety of hardware system
implementations, including multibus structures.

The objectives of this invention are:
  1.  Provide a hardware/software interface that allows the location
of
      individual registers which enable or disable the routing of
      interrupts to be located anywhere within the Architected System
      Memory space.  That is, to be implementation dependent.
  2.  Allow the communication between the hardware and the software
to
      be through an NVRAM interface, allowing a coprocessor to
actually
      communicate with the hardware.
  3.  Finally, allow the interface to support both 32-bit and 64-bit
      addressability implementations.

      Items (b) and (c) are discussed in [*].  To summarize, the
machine dependent access is via that Initial Program Load Control
Block (IPLCB) which is constructed during the Initial Program Load
(IPL) process, usually by the IPL Read Only Memory (ROM) code.  The
IPLCB contains an access_id and pointers to each item whose placement
is allowed to vary as a function of the machine.  Software uses the
access_id to determine if any special algorithms need to be performed
and the pointer is used on a 64-bit word machine by setting the upper
32-bits to all ones (restricting the placement of these facilities)
to the upper four (4) gigabytes of address space.

      Location independence of the interrupt routing masks (item a)
is addressed as follows.  The IPLCB contains a write address and bit
mask pair and a read address and bit mask pair.  With these two pairs
of parameters, software can read, turn on, and turn off any bit in
any location in the Architected System Memory space.  Software uses
these functions to communicated with the system hardware.
Specifically when the processor availability and interrupt routing is
controlled per processor bits in a control register, software can
control the availability status of any processor in a multi-processor
complex.

      By providing a separate write address and read address, the
interface allows for the software to monitor the time delay between
the commanding of a status change and its completion.  This is
particularly important if a maintainance processor actually
interfaces with the hardware.  With such a maintainance processor,
software sends commands via the write pair and determines actual
status by via the read pair.  This allows communication via any
shaired memory -- for example Non-Volital Random Access Memory
(NVRAM).  The actual support as described below allows the Global
Queue Interrupt Request Mask (GQ_IRM) support for a single global
queue for an SMP system with 32 processors to be...