Browse Prior Art Database

Hardware/Software Interface for Turning On/Off Processors in an Multiprocessor Environment

IP.com Disclosure Number: IPCOM000113647D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Arndt, RL: AUTHOR [+3]

Abstract

Disclosed is a hardware/software interface that allows software to turn on or off a processor. This support must work during IPL, but should also be expandable to work real time, that is, to support "hot plugging" a processor or turning a processor off-line without necessarily requiring a reset and a re-Initial Program Load (IPL) of the machine in future implementations. The indication of which processors to use on the next IPL may be used to prevent the turning on of a processor that causes a problem during IPL.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Hardware/Software Interface for Turning On/Off Processors in an Multiprocessor
Environment

      Disclosed is a hardware/software interface that allows software
to turn on or off a processor.  This support must work during IPL,
but should also be expandable to work real time, that is, to support
"hot plugging" a processor or turning a processor off-line without
necessarily requiring a reset and a re-Initial Program Load (IPL) of
the machine in future implementations.  The indication of which
processors to use on the next IPL may be used to prevent the turning
on of a processor that causes a problem during IPL.

The objectives of this invention are:
  1.  Provide a hardware/software interface that allows the location
of
      a mask which enables or disables the routing of interrupts to
be
      spread throughout the Architected System Memory space, that is,
      allows the location of the mask to be implementation dependent.
  2.  Allow the communication between the hardware and the software
to
      be through an Non-Volital Random Access Memory (NVRAM)
interface,
      allowing a coprocessor to actually communicate with the
hardware.
      This interface should allow for a software managed parity or
      Error Correcting Code (ECC) support.
  3.  Allow the interface to support both 32-bit and 64-bit
      addressability implementations.

Solution Summary - The machine dependent access is via the Initial
Program Load Control Block (IPLCB) which is constructed during the
IPL process, usually by the IPL Read Only Memory (ROM) code.  The
IPLCB contains an access_id and separate pointers to the write or
update address as distinguished from the read or verification
address.  Software uses the access_id to determine if any special
algorithms need to be performed and the pointer is used on a 64-bit
word machine by setting the upper 32-bits to all ones (restricting
the placement of these facilities) to the upper four (4) gigabytes of
address space.  The separation of the write address and the read
address is particularly important if NVRAM is used as a communication
vehicle and a coprocessor actually interfaces with the hardware, so
that software will have a mechanism to know if the change has
actually taken place.  In systems without a coprocessor, it may be
necessary to have a corresponding facility in the hardware, which
software has the responsibility of updating and verifying that the
update has occurred directly.

IPLCB Interface for Available Processor Mask (APM) Format:
  Byte    Length    Identifier               Description
        (in Bytes)
  0        4       num_processors    Number of Processors (N)
  4        4       access_id_waddr   Indication of type of write
access
  8        4       loc_waddr         Real Address of software write
                                ...