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Low Voltage Complementary Metal Oxide Semiconductor Differential Driver

IP.com Disclosure Number: IPCOM000113652D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Cao, T: AUTHOR [+4]

Abstract

This disclosure proposes a very high speed clock distribution driver for 400 MHZ, 200, 100 MHZ application. Several inhibit signals are provided for testability purposes. All are low voltage differential types of signals.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Low Voltage Complementary Metal Oxide Semiconductor Differential
Driver

      This disclosure proposes a very high speed clock distribution
driver for 400 MHZ, 200, 100 MHZ application.  Several inhibit
signals are provided for testability purposes.  All are low voltage
differential types of signals.

      Fig. 1 shows the clock distribution of Rio Bravo system.  All
the signals must adhere to the AC2 spec.  which comes from the
crystal oscillator chip.  The 400MHZ signal comes to the M-MDU(Master
Maintenance Device Unit) which in turn sends clock signals to three
different locations.  M-MDU is a part of the Switch section.  Within
Switch, the S-MDU(Slave Maintenance Device Unit) receives 200MHZ
clock signals from M-MDU.  Similarly, within Processor module, S-MDU
chip receives 400/200MHZ clock signals from M-MDU of switch side.  On
the memory card, a 200MHZ signal is also available from M-MDU.

      As shown in Fig. 1, the voltage swing of the clock signal
should be betwenn 1.5V(MPUL) and 0.5V(LPDL) with nominal crossing
point of two differential signals of 0.9V.  The driver is designed
for dual rail environment.  Because of dual rails, common-mode noise
rejection of receiver is very high which minimizes noise caused by
simultaneous switching and crosstalk.

      The proposed Complimentary Metal Oxide Semiconductor (CMOS)
differential driver for high speed clock application is shown in Fig.
2.  The output p devices Q1 and Q2, whose gates are tied to
respective drain sides to provide the proper logic '1' level of
differential outputs.  The constant current source n-device Q11
maintains a constant current flow from either leg of the output
signals.  The gate of Q11 is biased by the circuit network of devices
Q3, Q4, Q8 and Q9.  The n-device Q10 and Q12 in series with the
constant current source Q11 determine the logic '0' level and also
the falling transition of the output signals.  All the devices on the
output stages are lo...