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Structure of Complimentary Metal Oxide Semiconductor Gate Array Basic Cell

IP.com Disclosure Number: IPCOM000113656D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Oshikawa, H: AUTHOR

Abstract

This article describes a basic cell structure of a Complimentary Metal Oxide Semiconductor (CMOS) gate array. The structure simplifies metal wiring for a logic gate, by using a supplemental poly silicon wire in a basic cell.

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Structure of Complimentary Metal Oxide Semiconductor Gate Array Basic
Cell

      This article describes a basic cell structure of a
Complimentary Metal Oxide Semiconductor (CMOS) gate array.  The
structure simplifies metal wiring for a logic gate, by using a
supplemental poly silicon wire in a basic cell.

      Fig. 1 shows an example of this structure.  A metal wire (1)
connects transistor gates of pFET (2) and nFET (3).  Other metal
wires (4,5) and a poly-silicon wire (6) connect transistor gates of
other pFET (7) and nFET (8).  Fig. 2 shows the schematic of this
circuit.  The poly silicon of this wiring is a part of the described
basic cell.

      This structure of CMOS gate array basic cell reduces occupied
area by internal wiring, increases area for global wiring, and
improves circuits density.