Browse Prior Art Database

Wide Cache Tag Memory

IP.com Disclosure Number: IPCOM000113657D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Nakada, T: AUTHOR [+4]

Abstract

This article describes a memory configuration for a cache tag memory to enable the fast cache flush operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 59% of the total text.

Wide Cache Tag Memory

       Wide cache tag memory

      This article describes a memory configuration for a cache tag
memory to enable the fast cache flush operation.

      The flush operation for a write-back cache looks through all
the cache lines in order to find the dirty lines to be transferred
out.  The memory configuration described in this article makes it
faster by:
  1.  looking up the states of multiple cache lines simultaneously,
and
  2.  searching the dirty lines with apriority encoder.

      A conventional cache memory has a tag memory, each entry of
which corresponds to just one line of the data memory.  Every entry
of the tag memory consists of an address, a valid flag, and a dirty
flag.  If the dirty flag is set, the data in the data memory differs
from that in the main memory, and therefore it must be written back
to the main memory upon the cache flush.

      The tag memory described in this article is composed of the
address memory and the state memory, as shown in the Figure.  The
address memory has N entries, each of which contains the upper
portion of the address for the stored data.  The state memory has N/P
entries, each of which contains the cache line states, which are
governed by two flags, VALID (V) and DIRTY (D).  An entry of the
state memory has the states of P cache lines so that P states can be
read and written by one memory access.

      Using this memory configuration,  the cache flush operation
r...