Browse Prior Art Database

PowerPC 601 Microcode Completeness Methodology

IP.com Disclosure Number: IPCOM000113668D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Glenn, SC: AUTHOR [+3]

Abstract

Disclosed is a simulation methodology.for the PowerPC 601* microprocessor that determines functional coverage of the 1K ROS microcode implemented in the design.

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This is the abbreviated version, containing approximately 60% of the total text.

PowerPC 601 Microcode Completeness Methodology

      Disclosed is a simulation methodology.for the PowerPC 601*
microprocessor that determines functional coverage of the 1K ROS
microcode implemented in the design.

      This methodology was developed and implemented for Texsim
simulation using a combination of a custom C-program, special code or
trace hooks located within RTX, and assembly testcases.  RTX is a
pre-existing tool which allows RTPG testcases to run on a Texsim
simulation system model of the processor.

      The PowerPC 601's microcode is accessed using a 10-bit address
contained in the ROS Instruction Address Register (RIAR).  Trace
hooks were added within RTX to monitor and record all addresses
contained in the RIAR for each processor cycle that a given testcase
is simulated.  When simulation completes for a testcase, RTX creates
a 32X32 (1K) microcode address matrix containing a "1"  in locations
that were accessed or a "0" in locations that were not accessed.
This matrix is written to the testcase's SUMMARY file that is
returned to the testcase owner after simulation completes.   Thus,
each testcase simulated will return a unique matrix  for matrix2sum
to use as input.

      The C-Program, matrix2sum, reads all matrices returned from
simulation summary files, reads the PowerPC 601's microcode contents
for reference checks, and produces a summary matrix of all microcode
paths taken.  This summary matrix allows the verification expe...